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Structure Product Type Feature
Silicon monolithic integrated circuit Power management switch IC
BD6528HFV
Single channel of low on resistance (Typ = 110m) N-channel MOSFET built in Reverse-current protection when power switch off Output discharge circuit
Absolute maximum ratings (Ta=25) Parameter Supply voltage VIN voltage EN voltage VOUT voltage Storage temperature Power dissipation Symbol VDD VIN VEN VOUT TSTG Pd Rating -0.3 6.0 -0.3 6.0 -0.3 VDD + 0.3 -0.3 6.0 -55 150 849*1 Derating: 6.8mW/ above Ta = 25. Unit V V V V mW
*1 Mounted on 70mm * 70mm * 1.6mm glass-epoxy PCB.
* This product is not designed for protection against radioactive rays.
Operating conditions Parameter Operating voltage Switch input voltage Operating temperature Output current Symbol VDD VIN TOPR ILO MIN 2.7 0 -25 0 TYP MAX 4.5 2.7 85 500 Unit V V C mA
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Electric characteristics (Unless otherwise specified, VDD = 3.3V, VIN = 1.2V, Ta = 25C ) Limits Parameter Symbol MIN Operating current Standby current IDD ISTB VENH EN input voltage VENL EN input current ON resistance Switch leakage current Output turn on rise time Output turn on time Output turn off fall time Output turn off time Discharge ON resistance Discharge current IEN RON ILEAK TON1 TON2 TOFF1 TOFF2 RDISC IDISC -1.0 110 0.01 0.5 0.6 1 15 70 15 0.4 1.0 10 1.0 2.0 20 100 110 20 V A m A ms ms s s mA Low level input VEN = 0V or VEN = 1.2V IOUT = 500mA VEN = 0V, VOUT = 0V RL = 10 VOUT :10% 90% RL = 10 VEN High VOUT 90% RL = 10 VOUT :90% 10% RL = 10 VEN Low VOUT 10% IOUT = -1mA, VEN = 0V VOUT = 3.3V, VEN = 0V 1.2 TYP 20 0.01 MAX 30 1 A A V VEN = 1.2V VEN = 0V High level input Unit Condition
Switch output turn ON/OFF timing
Test circuit
VEN
50%
50%
TON2
TOFF2
VOUT RL
90% VOUT
90%
10% TON1
10% TOFF1
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Block diagram
Pin number, Pin name PIN number 1 2, 3 Pin Name GND VOUT VIN VDD EN Ground Switch output Switch input Power supply Enable input
Description
VIN VDD
VOUT
charge pump
GND EN
4 5 6
Package outline
BK
Lot No.
HVSOF6 (Unit: mm)
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Cautions on use (1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) Power supply and GND line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. Pay attention to the interference by common impedance of layout pattern when there are plural power supplies and GND lines. Especially, when there are GND pattern for small signal and GND pattern for large current included the external circuits, separate each GND pattern. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use a capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (3) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. (4) Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. (5) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. (6) Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (7) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. (8) Thermal design Perform thermal design in which there are adequate margins by taking into account the power dissipation (PD) in actual states of use.
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Notice
Notes
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